1. Field of the Invention
The present invention generally relates to a magnetic memory cell, and more particularly, to a multi-bit magnetic memory cell in a stacked structure and magnetic memory device using the same.
2. Description of Related Art
Magnetic memory, for example, Magnetic Random Access Memory (MRAM) has at least the advantages of non-volatile data storage, high storage density, high read/write speed and radiation resistant. Magnetic memory utilizes the magnetization of magnetic material adjacent to a tunnel barrier layer. The magnitude of magnetic resistance produced by a parallel and an anti-parallel arrangement can be used to record a data value of ‘0’ or ‘1’ in a memory cell. The conventional method of writing data into a memory cell includes using two current lines, for example, a Bit Line (BL) and a Write Word Line (WWL), to sense the memory cell of the magnetic memory selected by the crossover of magnetic fields. At the same time, changing the direction of magnetization of a free layer also changes the magneto-resistance value. To read data from the magnetic memory, a current is allowed to flow into the selected magnetic memory cell and the digital value of the memory data can be determined according to the reading of the magneto-resistance value.
FIG. 1 is a diagram showing the basic structure of a conventional magnetic memory cell. As shown in FIG. 1, accessing a magnetic memory cell needs a pair of crossover current lines 100 and 102 and each of the current lines 100 and 102 must be provided with a suitable current. According to the mode of operation, the current lines 100 and 102 are called a write word line and a write bit line, respectively. After currents are passed into the two conducting lines, magnetic fields in two directions are produced so that a magnetic field of the required magnitude and direction can be applied to the magnetic memory cell 104. The magnetic memory cell 104 has a stacked structure and includes a magnetic pinned layer having a fixed magnetization or total magnetic moment in a predetermined direction. The magnitude of the magnetic resistance can be used to determine the data. Furthermore, through the output electrodes 106 and 108, the data stored in the memory cell can be read. Since those skilled in the art should understand the details of operation of the magnetic memory, further description is omitted.
FIG. 2 shows a memory mechanism of a magnetic memory. As shown in FIG. 2, magnetic pinned layer 104a has a fixed magnetic moment direction 107. The free magnetic layer 104c is located above the magnetic pinned layer 104a and a barrier layer 104a in the middle isolates the two layers. This barrier layer 104b is also called a ‘tunnel barrier layer’. The free magnetic layer 104c has a magnetic moment direction 108a or 108b. Because the magnetic moment direction 107 is in parallel to the magnetic moment direction 108a, the generated magnetic resistance represents the data bit ‘0’, for example. Conversely, if the magnetic moment direction 107 is anti-parallel to the magnetic moment direction 108b, the generated magnetic resistance represents the data bit ‘1’, for example.
In general, when the free magnetic layer 104c is a single layer as shown in FIG. 2, the chance of having an accessing error is high. To resolve the problem and minimize the interference on adjacent memory cells when writing data, the conventional technique replaces the free magnetic layer with a single layer of ferromagnetic material by a ferromagnetic (FM)/non-magnetic metal (M)/ferromagnetic (FM) three-layered structure to form a stacked free magnetic layer 166. The stacked free magnetic layer 166 is shown in FIG. 3. The ferromagnetic metal layers 150 and 154 are disposed above and below the non-magnetic metal layer 152, respectively. The ferromagnetic metal layer 150 and the ferromagnetic metal layer 154 have an anti-parallel arrangement to form enclosed magnetic lines. The stacked magnetic pinned layer 168 below the stacked free magnetic layer 166 is isolated from the stacked free magnetic layer 166 by the tunnel barrier layer (T) 156. The stacked magnetic pinned layer 168 includes a top pinned layer (TP) 158, a non-magnetic metal layer 160 and a bottom pinned layer (BP) 162. Both the TP 158 and the BP 162 have a fixed magnetization. Furthermore, a base layer 164, for example, an anti-ferromagnetic layer, is disposed at the bottom.
For the stacked free magnetic layer 166 with three-layered structure, the Write Bit Line (WBL) and the Write Word Line (WWL) are disposed at 45° angle with respect to the magnetic anisotropic axis of the stacked free magnetic layer 166. The direction of the magnetic anisotropic axis is the so-called ‘easy axis direction’. Therefore, a magnetic field at 45° angle with respect to the easy axis can be respectively applied by the Write Bit Line (WBL) and the Write Word Line (WWL) according to a sequential relationship so as to rotate the magnetization of the stacked free magnetic layer 166. The directions of magnetization of the ferromagnetic metal layer 154 and the top pinned layer 158 also determine the data stored in the memory cell.
In addition to changing the single free layer to a three-layered structure, the conventional technique also provides a toggle mode of operation for rotating the magnetization of the free layer. Because the toggle mode operates by repeatedly switching between the bi-stable states ‘0’ and ‘1’, it is also called a bi-state mode. FIG. 4 is a diagram showing the effects of applying an external magnetic field on the three-layered structure. As shown in FIG. 4, the thick arrow represents an externally applied magnetic field. The length of the arrow represents the magnitude of the magnetic field. The two narrow arrows represent the magnetization direction of the top and bottom ferromagnetic layer of the stacked free layer. When the external magnetic field is too small, the two directions of magnetization remain unchanged. When the external magnetic field is increased beyond a threshold, the two directions of magnetization form an extension angle. When the external magnetic field is too large, the two directions of magnetization follow the direction of the external magnetic field. The operating point of the toggle mode belongs to the aforementioned second condition.
FIG. 5 is a timing diagram of external magnetic fields in the toggle mode. As shown in FIG. 5, H1 and H2 represent two external magnetic field directions at 45° angle with respect to the easy axis and the two arrows within the ellipse represent the two directions of the magnetization. In the time period t0, no external magnetic field is applied so that the two directions of magnetization are on the easy axis. Next, the magnetic fields H1 and H2 are enabled according to the timing in the diagram so as to obtain total magnetic field at different time periods (t1-t3) and rotate the two directions of magnetization. In the time period t4, no magnetic field is applied and the two directions of the magnetization are flipped over. In other words, the data stored in the memory cell is changed due to the writing.
In addition, the writing current is still high under the operating conditions of the toggle mode. Therefore, the conventional technique also provides the additional design of a bias magnetic field. FIG. 6 is a diagram showing the conventional technique of reducing the operating current. As shown by the diagram on the left side of FIG. 6, the basic structure of the memory cell is still similar to the one in FIG. 3. The main difference is that the total magnetic moment of the bottom pinned layer 162 is increased relative to the total magnetic moment of the top pinned layer 158, for example, by having a greater thickness. Due to an imbalance between the magnetic moment of the bottom pinned layer 162 and the top pinned layer 158, a stray magnetic field is produced. The stray magnetic field produces a bias field 184 on the stacked free magnetic layer 166 that can shift the toggle operating area of the first quadrant limit toward the zero point of the magnetic field, and as a result, is shortened to a distance 186. Therefore, since the required writing magnetic field is reduced, the current for producing a magnetic field in a write operation is also reduced.
In the above design, regardless of whether the operation is in the direct area or the toggle area (also called a binary state area), each memory cell has single bit storage capacity. Therefore, the conventional technique also provides a two-bit memory cell to increase memory storage capacity. FIG. 7 shows the circuit structure of conventional two-bit memory cells connected in parallel. As shown in FIG. 7, a two-bit memory cell includes two magnetic memory units 1100 and 1102 with each unit having a different magneto-resistance. Because the magneto-resistance of each magnetic memory unit has a largest and a smallest value, four different states can be assembled to achieve a two-bit memory storage capacity per cell. By controlling the measurement of the total magnetic resistance of the magnetic memory units 1100 and 1102 in parallel connection through a read bit line (RBL), for example, RBL01 and a read word line (RWL), for example, RWL1, the sense amplifier SA 1106 can read the total magnetic resistance when the transistor 1104 is conducting. After comparing the total magnetic resistance with a reference signal, the stored data D0 and D1 in the memory units are obtained. To write data into the memory units in the toggle operating mode, a write word line WWL1 and two write bit lines (WBL0, WBL1) are used as a group to control the magnetic memory units 1100 and 1102. The details of the operation are not described here.
FIG. 8 is a diagram showing the mechanism of a conventional two-bit magnetic memory cell. As shown in FIG. 8, for a two-bit magnetic memory cell operating in the toggle mode as shown in FIG. 7, the magnetic memory unit 1100 has a larger area for obtaining a smaller magneto-resistance value and the magnetic memory unit 1102 has a smaller area for obtaining a larger magneto-resistance value, for example. Because of the toggle mode of operation, the easy axis direction (the double arrow direction) is offset from the write bit line and the write word line by 45°.
FIG. 9 is a circuit diagram of a conventional two-bit magnetic memory cell. As shown in FIG. 9, with respect to the structure in FIG. 8, the magneto-resistance of the memory unit 1100 is R1 and the magneto-resistance of the memory unit 1102 is R2, and the resistance R1 and R2 are connected in parallel.
Because the foregoing two-bit magnetic memory cell design still has a horizontally stretch-out structure formed by using the area of the memory units. When the density of the memory cells is increased, this design occupies a larger usable surface area than other designs with the same memory capacity so that the potential for increasing the storage capacity is severely restricted.